Multi-core Design and Memory Feature Selection Survey

Due to increasing transistor density and the high complexity of core design, processor design has reached a point where multi-core architectures are nearly mandatory to push performance. Large single core designs entail problems such as clock skew and power leakage, while smaller fine tuned cores can run at a higher clock rates. Energy efficiency provides a strong drive for heterogeneous designs. A single all-purpose core running a computationally intensive application will have many components sitting idle and thus not provide good power to performance metrics. Similarly, any application that does not stress all aspects of the general purpose processor will not achieve good utilization of the available resources and thus waste power. In either homogeneous or heterogeneous core designs a common problem still remains: the CPU to memory gap. While our processors are capable of executing many instructions from many threads simultaneously, our memory systems are having a difficult time keeping up instruction and data fetch. With multi-core architectures dominating the market, further strain is placed on the memory system due to communicating threads and shared data. This paper is organized as follows. Section 2 will review some existing core designs. Section 3 will review recent work in both homogeneous and heterogeneous multi-core design. Section 4 will address some of the relevant work done in memory design pertaining to multi-core architectures. Section 5 will cover the merger between memory and processing in chip layout design called Processing In Memory. Section 6 will cover a few of the difficulties in simulating any proposed multi-core or multi-threaded design. Finally, Section 8 will summarize the current trends in design and propose an area of study.